1. Field of the Invention
The present invention relates to an exposure method for exposure of mask pattern on a photosensitive substrate in fabricating semiconductor devices etc., and an exposure system using the exposure method. Particularly, the invention is suitably applicable to the photolithography process wherein sequential exposures are effected in a layer as called as a middle layer not requiring a so high resolution, which is for example an ion-implanted layer used in fabricating semiconductor memories etc., and in a layer as called as a critical layer requiring a high resolution.
2. Related Background Art
The reduction projection exposure apparatus (steppers etc.) have been heretofore used in the photolithography process for fabricating the semiconductor devices such as VLSI, or liquid crystal displays etc. Generally, the semiconductor devices such as VLSI are formed by superimposing many patterns in layers on a wafer, and among those layers a layer requiring the highest resolution is called as a critical layer. In contrast with it, a layer not requiring a so high resolution, for example the ion-implanted layer used in fabricating semiconductor memories etc., is called as a middle layer. In other words, line widths of pattern in exposure in the middle layer are wider than those in exposure in the critical layer.
For example, recent VLSI fabrication plants often use separate exposure units for different layers each in its proper exposure in a fabrication process of a type of VLSI in order to enhance the throughput of fabrication steps. For example in the cases of fabricating VLSI having both the critical layer and the middle layer, a projection exposure apparatus with high resolution for critical layer was used also in exposure in the middle layer, or for exposure in the middle layer an exposure apparatus of the aligner type was used to effect full exposure on a single wafer. In the case of the former, an array (shot map) of shot areas in the middle layer was the same as that in the critical layer, whereby obviating the necessity to produce a new shot map for middle layer. Further, the latter also obviated the necessity to produce the shot map.
In the conventional technology as described above, the projection exposure apparatus for critical layer is ready for high resolutions. Therefore, when the exposure in the middle layer was effected by the projection exposure apparatus for critical layer, a reduction ratio of a projection optical system was too high, which narrows the field size, causing a problem of incapability to increase the throughput. Namely, the number of shot areas to be exposed on a wafer became too large with the narrow field size, requiring a longer exposure time in proportion to the number of shot areas. There was another problem that because the projection optical system with high resolution was expensive, the whole of the plural exposure units, used in fabricating a type of VLSI etc., became expensive.
When the exposure in the middle layer was conducted by the exposure apparatus of the aligner type, there was a problem that a sufficient resolution was not assured for large-scale wafers.
Also, high registration accuracy needs to be maintained in overlap exposures in different layers on VLSI. In order to enhance the registration accuracy as required, alignment marks (wafer marks) are formed in a predetermined array on a wafer, and alignment of wafer is carried out based on positions of these wafer marks. Accordingly, the time necessary for alignment also needs to be shortened in order to enhance the throughput of exposure steps.